1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly, to a technology capable of reducing the number of cell mats.
2. Related Art
A known semiconductor device consists of a plurality of memory cell arrays consisting of a plurality of unit cells. The plurality of memory cell arrays store and output data in response to an address. The semiconductor device also consists of a plurality of sense amplifier arrays configured to amplify a data signal output by a cell array and the sense amplifier outputs the amplified signal.
Recently, in order to improve competitiveness in the manufacturing cost of a semiconductor memory device, efforts to develop technologies for increasing a net die are made. As one of the technologies, there is proposed a technology for changing a cell array structure of 8F2 (i.e., an array occupying a 2F×4F=8F2 unit area or eight-square feature cell) into a cell array structure of 6F2 or 4F2. The cell array structure of 6F2 recently continues to be in the spotlight because more cells can be integrated per unit area compared to the cell array structure of 8F2.
In general, a folded bit line structure is applied to the cell array structure of 8F2, and an open bit line structure is applied to the cell array structure of 6F2. In this case, the folded bit line structure has a structure in which a bit line BL and a bit-bar line BLB are formed in parallel in one direction of a sense amplifier. The open bit line structure has a structure in which a bit line and a bit-bar line are separated on both sides of a sense amplifier.